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| FEATURES s s LTC1922-1 Synchronous Phase Modulated Full-Bridge Controller DESCRIPTIO The LTC(R)1922-1 phase shift PWM controller provides all of the control and protection functions necessary to implement a high performance, zero voltage switched, phase shift, full-bridge power converter with synchronous rectification. The part is ideal for developing isolated, low voltage, high current outputs from a high voltage input source. The LTC1922-1 combines the benefits of the fullbridge topology with fixed frequency, zero voltage switching operation (ZVS). Adaptive ZVS circuity controls the turn-on signals for each MOSFET independent of internal and external component tolerances for optimal performance. The LTC1922-1 also provides secondary side synchronous rectifier control. The device uses peak current mode control with programmable slope comp and leading edge blanking. The LTC1922-1 features extremely low operating and start-up currents to simplify off-line start-up and bias circuitry. The LTC1922-1 also includes a full range of protection features and is available in 20-pin through hole (N) and surface mount (G) packages. , LTC and LT are registered trademarks of Linear Technology Corporation. DirectSense is a trademark of Linear Technology Corporation. s s s s s s s s s s Adaptive DirectSenseTM Zero Voltage Switching Integrated Synchronous Rectification Control for Highest Efficiency Output Power Levels from 50W to Kilowatts Very Low Start-Up and Quiescent Currents Compatible with Voltage Mode and Current Mode Topologies Programmable Slope Compensation Undervoltage Lockout Circuitry with 4.2V Hysteresis and Integrated 10.3V Shunt Regulator Fixed Frequency Operation to 1MHz 50mA Outputs for Bridge Drive and Secondary Side Synchronous Rectifiers Soft-Start, Cycle-by-Cycle Current Limiting and Hiccup Mode Short-Circuit Protection 5V, 15mA Low Dropout Regulator 20-Pin PDIP and SSOP Packages APPLICATIO S s s s s Telecommunications, Infrastructure Power Systems Distributed Power Architectures Server Power Supplies High Density Power Modules TYPICAL APPLICATIO BIAS SUPPLY VIN 48V VOUT 3.3V EFFICIENCY (%) LTC1922-1 ISOLATED FEEDBACK 1922 TA01a U U U Efficiency 100 90 VIN = 48V VIN = 36V 80 70 60 0 10 20 LOAD CURRENT (A) 30 40 1922 * TA01b 1 LTC1922-1 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW SYNC RAMP CS COMP RLEB FB SS PDLY SBUS 1 2 3 4 5 6 7 8 9 20 CT 19 GND 18 OUTA 17 OUTB 16 OUTC 15 VCC 14 OUTD 13 OUTE 12 OUTF 11 VREF N PACKAGE 20-LEAD PDIP VCC to GND Low Impedance Source ......................... -0.3V to 10V (Chip Self Regulates at 10.3V) All Other Pins to GND (Low Impedance Source) ..................... -0.3V to 5.5V VCC (Current Fed) .................................................. 25mA VREF Output Current ................................ Self Regulated Outputs (A, B, C, D, E, F) Current ..................... 100mA Operating Temperature Range (Note 5) LTC1922E ........................................... - 40C to 85C LTC1922I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 125C Lead Temperature (Soldering, 10 sec).................. 300C ORDER PART NUMBER LTC1922EG-1 LTC1922IG-1 LTC1922EN-1 LTC1922IN-1 ADLY 10 G PACKAGE 20-LEAD PLASTIC SSOP TJMAX = 125C, JA = 110C/W (G) TJMAX = 125C,JA = 62C/W (N) Consult factory for parts specified with wider operating temperature ranges. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VCC = 9.5V, CT = 180pF, TA = TMIN to TMAX unless other wise noted. SYMBOL Input Supply UVLO UVHY ICCST ICCRN VSHUNT RSHUNT Delay Blocks DTHR DHYS DTMO DZRT Phase Modulator ROS IRMP ISLP DCMX DCMN RAMP Offset Voltage RAMP Discharge Current Slope Compensation Current Maximum Phase Shift Minimum Phase Shift Measured on COMP, RAMP = 0V RAMP = 1V, COMP = 0V Measured on CS, CT = 1.5V CT = 3V COMP = 4V COMP = 0V q q ELECTRICAL CHARACTERISTICS PARAMETER Undervoltage Lockout UVLO Hysteresis Start-Up Current Operating Current Shunt Regulator Voltage Shunt Resistance Delay Pin Threshold ADLY and PDLY Delay Hysteresis Current ADLY and PDLY Delay Time-Out Zero Delay Threshold CONDITIONS Measured on VCC Measured on VCC VCC = VUVLO - 0.3V Current Into VCC = 10mA Current Into VCC = 7mA to 17mA SBUS = 1.5V SBUS = 2.25V SBUS = 1.5V, ADLY/PDLY = 1.6V SBUS = 1.5V SBUS = 2.25V Measured on SBUS q MIN TYP 10.25 MAX 10.7 250 7 10.8 2 1.62 2.42 1.45 UNITS V V A mA V V V mA ns ns 3.8 4.2 145 4 10.2 -1.5 1.38 2.08 1.1 1.50 2.25 1.3 600 900 3 4.15 0.4 5 30 35 70 95 50 55 110 99.5 0.1 0.6 75 150 2 U V V mA A A % % W U U WW W LTC1922-1 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VCC = 9.5V, CT = 180pF, TA = TMIN to TMAX unless other wise noted. SYMBOL Oscillator OSCT OSCV OSYT OSYW OSYWX OSOP Error Amplifier VFB FBI AVOL IIB VOH VOL ISOURCE ISINK Reference VREF REFTV REFLD REFLN REFSC Outputs OUTH(X) OUTL(X) RHI(X) RLO(X) tr(X) tf(X) CLPP CLSD SSI SSR FLT Output High Voltage Output Low Voltage Pull-Up Resistance Pull-Down Resistance Rise Time Fall Time Pulse-by-Pulse Current Limit Threshold Shutdown Current Limit Threshold Soft-Start Current Soft-Start Reset Threshold FAULT Reset Threshold IOUT(X) = -50mA IOUT(X) = 50mA IOUT(X) = -50mA to -10mA IOUT(X) = -50mA to -10mA COUT(X) = 50pF COUT(X) = 50pF Measured on CS Measured on CS SS = 2.5V Measured on SS Measured on SS 0.34 0.55 7 0.7 4.4 7.9 8.4 0.6 22 12 5 5 0.415 0.64 12 0.4 4.1 1 30 20 15 15 0.48 0.73 17 0.1 3.8 V V ns ns V V A V V Initial Accuracy Total Variation Load Regulation Line Regulation Short-Circuit Current TA = 25C, Measured on VREF Line, Load and Temperature Load on VREF = 100A to 5mA VCC = 6.5V to 9.5V VREF Shorted to GND 18 q ELECTRICAL CHARACTERISTICS PARAMETER Total Variation CT RAMP Amplitude SYNC Threshold Minimum SYNC Pulse Width Maximum SYNC Pulse Width SYNC Output Pulse Width FB Input Voltage FB Input Range Open-Loop Gain Input Bias Current Output High Output Low Output Source Current Output Sink Current CONDITIONS VCC = 6.5V to 9.5V Measured on CT Measured on SYNC Measured at Outputs (Note 2) Measured on Outputs, CT = 180pF Measured on SYNC, RSYNC = 5.1k COMP = 2.5V (Note 3) Measured on FB (Note 4) COMP = 1V to 3V (Note 3) COMP = 2.5V (Note 3) Load on COMP = -100A Load on COMP = 100A COMP = 2.5V COMP = 2.5V q MIN 236 3.6 1.6 TYP 277 3.85 1.8 6 MAX 319 4.2 2.2 1.3 UNITS kHz V V ns s ns 170 1.179 -0.3 70 4.7 - 400 3 4.925 4.9 90 5 4.92 0.18 - 800 7 5 5 2 0.1 30 5.075 5.1 15 10 45 0.4 50 1.204 1.229 2.5 V V dB nA V V A mA V V mV mV mA Current Limit and Shutdown Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: SYNC pulse width is valid from >20ns and <0.4 * (1/fOSC), VSYNC = 0V to 5V. Note 3: FB is driven by a servo loop amplifier to control VCOMP for these tests. Note 4: Set FB to -0.3V, 2.5 and insure that COMP does not phase invert. Note 5: The LTC1922-1E is guaranteed to meet performance specifications from 0C to 85C. Specification over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC1922-1I is guaranteed and tested over the - 40C to 85C operating temperature range. 3 LTC1922-1 TYPICAL PERFOR A CE CHARACTERISTICS Start-Up ICC vs VCC 200 TA = 25C 150 FREQUENCY (kHz) ICC (A) VCC (V) 100 50 0 0 2 4 VCC (V) 6 Leading Edge Blanking Time vs RLEB 350 300 250 BLANK TIME (ns) TA = 25C 200 150 100 VREF (V) 50 0 0 10 20 30 40 50 60 RLEB (k) 70 80 90 100 1922 * G04 VREF vs Temperature 5.01 100 80 60 40 20 0 -180 -270 -360 GAIN (dB) 5.00 VREF (V) 4.99 PHASE (DEG) 4.98 4.97 - 60 - 40 - 20 0 20 40 60 TEMPERATURE (C) 4 UW 8 1922 * G01 VCC vs ISHUNT 10.50 TA = 25C 280 Oscillator Frequency vs Temperature CT = 180pF 270 10.25 10.00 260 9.75 250 9.50 10 0 10 30 20 ISHUNT (mA) 40 50 1922 * G02 240 - 60 - 40 - 20 0 20 40 60 TEMPERATURE (C) 80 100 1922 * G03 VREF vs IREF 5.05 TJ = 25C TJ = 85C 4.95 5.00 4.90 TJ = -40C 4.85 4.80 0 5 10 15 20 25 IREF (mA) 30 35 40 1922 * G05 Error Amplifier Gain/Phase TA = 25C 80 100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 1922 * G03 1922 * G07 LTC1922-1 TYPICAL PERFOR A CE CHARACTERISTICS Start-Up ICC vs Temperature 160 150 1.278 1.276 1.274 1.272 HYSTERESIS CURRENT (mA) 140 130 CURRENT (A) ICC (A) 120 110 100 90 80 70 -55 -25 5 35 65 TEMPERATURE (C) 95 125 VCC Shunt Voltage vs Temperature 10.5 ICC = 10mA 10.4 2.4 2.3 2.2 SHUNT VOLTAGE (V) 10.3 THRESHOLD (V) 10.2 10.1 10.0 9.9 9.8 -55 -25 FB Input Voltage vs Temperature 1.202 1.201 1.200 390 385 380 FB VOLTAGE (V) OFFSET (mV) 1.199 1.198 1.197 1.196 1.195 1.194 -55 -25 5 35 65 TEMPERATURE (C) 95 125 UW 1922 * G10 Delay Hysteresis Current vs Temperature SBUS = 1.5V 130 120 110 100 90 80 70 60 50 40 -25 5 35 65 TEMPERATURE (C) 95 125 Slope Current vs Temperature CT = 3.0V 1.270 1.268 1.266 1.264 1.262 1.260 1.258 1.256 -55 CT = 1.5V -55 -25 5 35 65 TEMPERATURE (C) 95 125 1922 * G11 1922 * G12 Delay Pin Threshold vs Temperature SBUS = 2.25V 2.1 2.0 1.9 1.8 1.7 1.6 1.5 SBUS = 1.5V 5 35 65 TEMPERATURE (C) 95 125 1.4 -55 -25 5 35 65 TEMPERATURE (C) 95 125 1922 * G13 1922 * G14 Ramp Offset Voltage vs Temperature 375 370 365 360 355 350 -55 -25 5 35 65 TEMPERATURE (C) 95 125 1922 * G15 1922 * G16 5 LTC1922-1 PIN FUNCTIONS SYNC (Pin 1): Synchronization Input/Output for the Oscillator. Terminate SYNC with a 5.1k resistor to GND. RAMP (Pin 2): Input to Phase Modulator Comparator. The voltage on RAMP is internally level shifted by 400mV. CS (Pin 3): Input to Current Limit Comparators, Output of Slope Compensation Circuitry. COMP (Pin 4): Error Amplifier Output, Input to Phase Modulator. RLEB (Pin 5): Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor to program from 40ns to 310ns of leading edge blanking. A 1% tolerance resistor is recommended. Leading edge blanking may be defeated by connecting RLEB to VREF. FB (Pin 6): Error Amplifier Inverting Input. This is the voltage feedback input for the LTC1922-1. SS (Pin 7): Soft-Start/Restart Delay Circuitry Timing Capacitor. PDLY (Pin 8): Passive Leg Delay Circuit Input. SBUS (Pin 9): Input (Bus) Voltage Sensing Input. ADLY (Pin 10): Active Leg Delay Circuit Input. VREF (Pin 11): 5V Reference Output. VREF is capable of supplying up to 15mA to external circuitry. Bypass VREF with a 1F (minimum) ceramic capacitor to GND. OUTF (Pin 12): 50mA Driver Output for Secondary Side Current Doubler Synchronous Rectifier. OUTE (Pin 13): 50mA Driver Output for Secondary Side Current Doubler Synchronous Rectifier. OUTD (Pin 14): 50mA Driver Output for Active Leg Low Side. VCC (Pin 15): Chip Power Supply Input, 10.3V Shunt Regulator. Bypass VCC with a 0.1F or larger ceramic capacitor to GND. OUTC (Pin 16): 50mA Driver Output for Active Leg High Side. OUTB (Pin 17): 50mA Driver Output for Passive Leg Low Side. OUTA (Pin 18): 50mA Driver Output for Passive Leg High Side. GND (Pin 19): All Voltages on the LTC1922-1 Are Referred to GND. CT (Pin 20): Timing Capacitor for Oscillator. Use 5% or better multilayer NPO ceramic for best results. 6 U U U LTC1922-1 BLOCK DIAGRA UVLO SHUNT REG 10.25V "ON" 6V "0FF" ERROR AMPLIFIER FB 6 1.2V COMP 4 - + RAMP 2 BLANK QB VREF 12A Q R S 13 OUTE SYNC RECTIFIER DRIVE LOGIC SS 7 + 600mV RLEB 5 - CS 3 BLANK 400mV TI I G DIAGRA W W VCC 15 VREF 11 CT 20 SYNC 1 SBUS 9 5V REF AND LDO OSC 1.2V 8 PDLY 50k PHASE MODULATOR - + Q T QB 0.4V 14.9k PASSIVE DELAY 17 OUTB 18 OUTA + - 12 OUTF FAULT LOGIC R S QB ACTIVE DELAY 14 OUTD SLOPE COMPENSATION CT/R 19 16 OUTC SHUTDOWN CURRENT LIMIT + - 10 ADLY GND 1922 * BD PULSE BY PULSE CURRENT LIMIT UW ACTIVE DELAY PASSIVE DELAY OUTA OUTB OUTC OUTD RAMP COMP CURRENT DOUBLER OUTE OUTF NOTE: SHADED AREAS CORRESPOND TO POWER DELIVERY PULSES 1922 TD 7 LTC1922-1 OPERATIO Phase Shift Full-Bridge PWM Conventional full-bridge switching power supply topologies are often employed for high power, isolated DC/DC and off-line converters. Although they require two additional switching elements, substantially greater power and higher efficiency can be attained for a given transformer size compared to the more common single-ended forward and flyback converters. These improvements are realized since the full-bridge converter delivers power during both parts of the switching cycle, reducing transformer core loss and lowering voltage and current stresses. The fullbridge converter also provides inherent automatic transformer flux reset and balancing due to its bidirectional drive configuration. As a result, the maximum duty cycle range is extended, further improving efficiency. Soft switching variations on the full-bridge topology have been proposed to improve and extend its performance and application. These zero voltage switching (ZVS) techniques exploit the generally undesirable parasitic elements present within the power stage. The parasitic elements are utilized to drive near lossless switching transitions for all of the external power MOSFETs. LTC1922-1 phase shift PWM controller provides enhanced performance and simplifies the design task required for a ZVS phase shifted full-bridge converter. The primary attributes of the LTC1922-1 as compared to currently available solutions include: 1) Truly adaptive and accurate (DirectSense technology) ZVS switching delays. Benefit: higher efficiency, higher duty cycle capability, eliminates external trim. 2) Internally generated drive signals for current doubler synchronous rectifiers. Benefit: eliminates external glue logic, drivers, optimal timing for highest efficiency. 3) Programmable (single resistor) leading edge blanking. Benefit: prevents spurious operation, reduces external filtering required on CS. 4) Programmable (single resistor) slope compensation. Benefit: eliminates external glue circuitry. Switching Transitions The phase shifted full-bridge can be described by four primary operating states. The key to understanding how ZVS occurs is revealed by examining the states in detail. 8 U 5) Optimized current mode control architecture. Benefit: eliminates glue circuitry, less overshoot at startup, faster recovery from system faults. 6) Proven reference circuits and design tools. Benefit: substantially reduced learning curve, more time for optimization. As a result, the LTC1922-1 makes the ZVS topology feasible for a wider variety of applications, including those at lower power levels. The LTC1922-1 controls four external power switches in a full-bridge arrangement. The load on the bridge is the primary winding of a power transformer. The diagonal switches in the bridge connect the primary winding between the input voltage and ground every oscillator cycle. The pair of switches that conduct are alternated by an internal flip-flop in the LTC1922-1. Thus, the voltage applied to the primary is reversed in polarity on every switching cycle and each output drive signal is 1/2 the frequency of the oscillator. The on-time of each driver signal is slightly less that 50%. The actual percentage is adaptively modulated by the LTC1922-1. The on-time overlap of the diagonal switch pairs is controlled by the LTC1922-1 phase modulation circuitry. (Refer to Block and Timing Diagrams) This overlap sets the approximate duty cycle of the converter. The LTC1922-1 driver output signals (OUTA to OUTF) are optimized for interface with an external gate driver IC or buffer. External power MOSFETs A and C require high side driver circuitry, while B and D are ground referenced and E and F are ground referenced but on the secondary side of the isolation barrier. Methods for providing drive to these elements are detailed in the data sheet. The secondary voltage of the transformer is the primary voltage divided by the transformer turns ratio. Similar to a buck converter, the secondary square wave is applied to an output filter inductor and capacitor to produce a well regulated DC output voltage. LTC1922-1 OPERATIO Each full cycle of the transformer has two distinct periods in which power is delivered to the output, and two "freewheeling" periods. The two sides of the external bridge have fundamentally different operating characteristics that become important when designing for ZVS over a wide load current range. The left bridge leg is referred to as the "passive" leg, while the right leg is referred to as the "active" leg. The following descriptions provide insight as to why these differences exist. State 1 (Power Pulse 1) Referring to Figure 1, State 1 begins with MA, MD and MF "ON" and MB, MC and ME "OFF." During the simultaneous conduction of MA and MD, the full input voltage is applied across the transformer primary winding and following the dot convention, VIN/N is applied to the left side of LO1 allowing current to increase in LO1. The primary current during this period is approximately equal to the output inductor current (LO1) divided by the transformer turns ratio plus the transformer magnetizing current (VIN * tON/ LMAG). MD turns off and ME turns on at the end of State 1. State 2 (Active Transition and Freewheel Interval) MD turns off when the phase modulator comparator transitions. At this instant, the voltage on the MD/MC junction begins to rise towards the applied input voltage (VIN). The transformer's magnetizing current and the reflected output inductor current propels this action. The slew rate is limited by MOSFET MC and MD's output capacitance (COSS), snubbing capacitance and the transformer interwinding capacitance. The voltage transition on the active leg from the ground reference point to VIN will always occur, independent of load current as long as energy in the transformer's magnetizing and leakage inductance is greater than the capacitive energy. That is, 1/2 * (LM + LI) * IM2 > 1/2 * 2 * COSS * VIN2 -- the worst case occurs when the load current is zero. This condition is usually easy to meet. The magnetizing current is virtually constant during this transition because the magnetizing inductance has positive voltage applied across it throughout the low to high transition. Since the leg is actively driven by this "current source," it is called the active or linear transition. When the voltage on the active leg has U risen to VIN, MOSFET MC is switched on by the LTC19221 DirectSense circuitry. The primary current now flows through the two high side MOSFETs (MA and MC). The transformer's secondary windings are electrically shorted at this time since both ME and MF are "ON". As long as positive current flows in LO1 and LO2, the transformer primary (magnetizing) inductance is also shorted through normal transformer action. MA and MF turn off at the end of State 2. State 3 (Passive Transition) MA turns off when the oscillator timing period ends, i.e., the clock pulse toggles the internal flip-flop. At the instant MA turns off, the voltage on the MA/MB junction begins to decay towards the lower supply (GND). The energy available to drive this transition is limited to the primary leakage inductance and added commutating inductance which have (IMAG + IOUT/2N) flowing through them initially. The magnetizing and output inductors don't contribute any energy because they are effectively shorted as mentioned previously, significantly reducing the available energy. This is the major difference between the active and passive transitions. If the energy stored in the leakage and commutating inductance is greater than the capacitive energy, the transition will be completed successfully. During the transition, an increasing reverse voltage is applied to the leakage and commutating inductances, helping the overall primary current to decay. The inductive energy is thus resonantly transferred to the capacitive elements, hence, the term passive or resonant transition. Assuming there is sufficient inductive energy to propel the bridge leg to GND, the time required will be approximately equal to * LC/2. When the voltage on the passive leg nears GND, MOSFET MB is commanded "ON" by the LTC1922-1 DirectSense circuitry. Current continues to increase in the leakage and external series inductance which is opposite in polarity to the reflected output inductor current. When this current is equal in magnitude to the reflected output current, the primary current reverses direction, the opposite secondary winding becomes forward biased and a new power pulse is initiated. The time required for the current reversal reduces the effective maximum duty cycle 9 LTC1922-1 OPERATIO a . nd must be considered when specifying the power transformer. If ZVS is required over the entire range of loads, a small commutating inductor is added in series with the primary to aid with the passive leg transition, since the leakage inductance alone is usually not sufficient and predictable enough to guarantee ZVS over the full load range. State 1. State 2. State 3. State 4. 10 U State 4 (Power Pulse 2) During power pulse 2, current builds up in the primary winding in the opposite direction as power pulse 1. The primary current consists of reflected output inductor current and current due to the primary magnetizing inductance. At the end of State 4, MOSFET MC turns off and an active transition, essentially similar to State 2, but opposite in direction (high to low) takes place. POWER PULSE 1 VIN L1 MA MC N:1 MB MD MF ME L2 LOAD VOUT + IP IL01/N + (VIN * TOVL)/LMAG PRIMARY AND SECONDARY SHORTED ACTIVE TRANSITION FREEWHEEL INTERVAL VOUT MA MC MA MC LOAD MB MD MB MD MF ME PASSIVE TRANSITION MA MC MB MD POWER PULSE 2 VOUT MA MC LOAD MB MD MF ME + 1922 F01 Figure 1. ZVS Operation LTC1922-1 OPERATIO Zero Voltage Switching (ZVS) A lossless switching transition requires that the respective full-bridge MOSFETs be switched to the "ON" state at the exact instant their drain to source voltage is zero. Delaying the turn-on results in lower efficiency due to circulating current flowing in the body diode of the primary side MOSFET rather than its low resistance channel. Premature turn-on produces hard switching of the MOSFETs, increasing noise and power dissipation. Previous solutions have attempted to meet these requirements with fixed or first order (linear) variable open-loop time delays. Openloop methods typically set the turn-on delay to the worst case longest bridge transition time expected plus the tolerances of all the internal and external delay timing circuitry. These error tolerances can be quite significant, while the optimal transition times over the load current range vary nonlinearly. In a volume production environment, these factors can necessitate an external trim to guarantee ZVS operation, adding cost to the final product. An additional side effect of longer than required delays is a decrease in the effective maximum duty cycle. Reduced duty cycle range can mandate a lower transformer turns ratio, impacting efficiency or requiring a lower switching frequency, impacting size. LTC1922-1 Adaptive Delay Circuitry The LTC1922-1 addresses the issue of nonideal switching delays with novel DirectSense circuitry that intelligently monitors both the input supply and instantaneous bridge leg voltages, and commands a switching transition when the expected zero voltage condition is reached. In effect, the LTC1922-1 "closes the loop" on the ZVS turn-on delay requirements. DirectSense technology provides optimal turn-on delay timing, regardless of input voltage, output load, or component tolerances and greatly simplifies the power supply design process. The DirectSense technique requires only a simple voltage divider sense network to implement. If there is not enough energy to fully commutate the bridge leg to a ZVS condition, the LTC1922-1 automatically overrides the DirectSense circuitry and forces a transition. The LTC1922-1 delay circuitry can also be overridden, by tying SBUS to VREF. U Adaptive Mode The LTC1922-1 is configured for adaptive delay sensing with three pins, ADLY, PDLY and SBUS. ADLY and PDLY sense the active and passive delay legs respectively via a voltage divider network as shown in Figure 2. VIN R2 SBUS R5 PDLY B R1 R3 1k RCS 1922 F02 A C ADLY R6 D R4 1k Figure 2. Adaptive Mode The threshold voltage on PDLY and ADLY for both the rising and falling transitions is set by the voltage on SBUS. A buffered version of this voltage is used as the threshold level for the internal DirectSense circuitry. At nominal VIN, the voltage on SBUS is set to 1.5V by an external voltage divider between VIN and GND, making this voltage directly proportional to VIN. The LTC1922-1 DirectSense circuitry uses this characteristic to zero voltage switch all of the external power MOSFETs, independent of input voltage. ADLY and PDLY are connected through voltage dividers to the active and passive bridge legs respectively. The lower resistor in the divider is set to 1k. The upper resistor in the divider is divided into one, two or three equal value resistors to reduce its overall capacitance. In off-line applications, this is usually required anyway to stay within the maximum voltage ratings of the resistors. One or two resistor segments will work for most nominal 48V or lower VIN applications. To set up the ADLY and PDLY resistors, first determine at what drain to source voltage to turn-on the MOSFETs. Finite delays exist between the time at which the LTC1922-1 controller output transitions, to the time at which the power MOSFET switches on due to MOSFET turn on delay and external driver circuit delay. Ideally, we want the power MOSFET to switch at the instant there is zero volts across it. By setting a threshold voltage for ADLY and 11 LTC1922-1 OPERATIO PDLY corresponding to several volts across the MOSFET, the LTC1922-1 can "anticipate" a zero voltage VDS and signal the external driver and switch to turn-on. The amount of anticipation can be tailored for any application by modifying the upper divider resistor(s). The LTC1922-1 DirectSense circuitry sources a trimmed current out of PDLY and ADLY after a low to high level transition occurs. This provides hysteresis and noise immunity for the PDLY and ADLY circuitry, and sets the high to low threshold on ADLY or PDLY to nearly the same level as the low to high threshold, thereby making the upper and lower MOSFET VDS switch points virtually identical, independent of VIN. Example: VIN = 48V nominal (36V to 72V) 1. Set up SBUS: 1.5V is desired on SBUS with VIN = 48V. Set divider current to 100A. R1 = 1.5V/100A = 15k. R2 = (48V - 1.5V)/100A = 465k. An optional small capacitor (0.001F) can be added across R1 to decouple noise from this input. 2. Set up ADLY and PDLY: 7V of "anticipation" are required in this circuit to account for the delays of the external MOSFET driver and gate drive components. R3, R4 = 1k, sets a nominal 1.5mA in the divider chain at the threshold. R5, R6 = (48V - 7V - 1.5V)/1.5mA = 26.3k, use (2) equal 13k segments. Zero Delay Mode The LTC1922-1 provides the flexibility through the SBUS pin to disable the DirectSense delay circuitry. See Figure 3 for details. VREF SBUS Powering the LTC1922-1 The LTC1922-1 utilizes an integrated VCC shunt regulator to serve the dual purposes of limiting the voltage applied VCC VCC 1922 F04 12 U to VCC as well as signaling that the chip's bias voltage is sufficient to begin switching operation (under voltage lockout). With its typical 10.2V turn-on voltage and 4.2V UVLO hysteresis, the LTC1922-1 is tolerant of loosely regulated input sources such as an auxiliary transformer winding. The VCC shunt is capable of sinking up to 25mA of externally applied current. The UVLO turn-on and turnoff thresholds are derived from an internally trimmed reference making them extremely accurate. In addition, the LTC1922-1 exhibits very low (145A typ) start-up current that allows the use of 1/8W to 1/4W trickle charge start-up resistors. The trickle charge resistor should be selected as follows: RSTART(MAX) = VIN(MIN) - 10.7V/250A Adding a small safety margin and choosing standard values yields: APPLICATION DC/DC Off-Line PFC Preregulator VIN RANGE 36V to 72V 85V to 270VRMS 390VDC RSTART 100k 430k 1.4M VCC should be bypassed with a 0.1F to 1F multilayer ceramic capacitor to decouple the fast transient currents demanded by the output drivers and a bulk tantalum or electrolytic capacitor to hold up the VCC supply before the bootstrap winding, or an auxiliary regulator circuit takes over. CHOLDUP = (ICC + IDRIVE) * tDELAY/3.8V (minimum UVLO hysteresis) Regulated bias supplies as low as 7V can be utilized to provide bias to the LTC1922-1. Refer to Figure 4 for various bias supply configurations. VIN 12V 10% VBIAS < VUVLO 1N5226 3V 1N914 RSTART ADLY PDLY 1922 F03 1.5k Figure 3. Zero Delays 0.1F + 0.1F CHOLD Figure 4. Bias Configurations LTC1922-1 OPERATIO Off-Line Bias Supply Generation If a regulated bias supply is not available to provide VCC voltage to the LTC1922-1 and supporting circuitry, one must be generated. Since the power requirement is small, approximately 1W, and the regulation is not critical, a simple open-loop method is usually the easiest and lowest cost approach. One method that works well is to add a winding to the main power transformer, and post regulate the resultant square wave with an L-C filter (see Figure 5a). The advantage of this approach is that it maintains decent regulation as the supply voltage varies, and it does not require full safety isolation from the input winding of the transformer. Some manufacturers include a primary winding for this purpose in their standard product offerings as well. A different approach is to add a winding to the output inductor and peak detect and filter the square wave signal (see Figure 5b). The polarity of this winding is designed so that the positive voltage square wave is produced while the output inductor is freewheeling. An advantage of this technique over the previous is that it does not require a separate filter inductor and since the voltage is derived from the well-regulated output voltage, it is also well controlled. One disadvantage is that this winding will require the same safety isolation that is required for the main transformer. Another disadvantage is that a much larger VCC filter capacitor is needed, since it does not VIN RSTART VCC Figure 5a. Auxiliary Winding Bias Supply VIN LOUT RSTART ISO BARRIER VOUT VCC Figure 5b. Output Inductor Bias Supply U generate a voltage as the output is first starting up, or during short-circuit conditions. Programming the LTC1922-1 Oscillator The high accuracy LTC1922-1 oscillator circuit provides flexibility to program the switching frequency, slope compensation, and synchronization with minimal external components. The LTC1922-1 oscillator circuitry produces a 3.8V peak-to-peak amplitude ramp waveform on CT and a narrow pulse on SYNC that can be used to synchronize other PWM chips. Typical maximum duty cycles of 99% are obtained at 300kHz and 97% at 1MHz. The large amplitude ramp provides a high degree of noise margin. A compensating slope current is derived from the oscillator ramp waveform and sourced out of CS. The desired amount of slope compensation is selected with single external resistor (or no resistor), if not required. A capacitor to GND on CT programs the switching frequency. The CT ramp discharge current is internally set to a high value (>10mA). The dedicated SYNC I/O pin easily achieves synchronization. The LTC1922-1 can be set up to either synchronize other PWM chips or be synchronized by another chip or external clock source. The 1.8V SYNC threshold allows the LTC1922-1 to be synchronized directly from all standard 3V and 5V logic families. Design Procedure: 1. Choose CT for the desired oscillator frequency. The switching frequency selected must be consistent with the power magnetics and output power level. This is detailed in the Transformer Design section. In general, increasing the switching frequency will decrease the maximum achievable output power, due to limitations of maximum duty cycle imposed by transformer core reset and ZVS. Remember that the output frequency is 1/2 that of the oscillator. CT = 1/(20k * fOSC) Example: Desired fOSC = 330kHz 0.1F CHOLD + 15V* CHOLD 2k 0.1F 1922 F05a *OPTIONAL + 1922 F05b CT = 1/(20k * 330kHz) = 152pF, choose closest standard value of 150pF. A 5% or better tolerance multilayer NPO or X7R ceramic capacitor is recommended for best performance. 13 LTC1922-1 OPERATIO 2. The LTC1922-1 can either synchronize other PWMs, or be synchronized to an external frequency source or PWM chip. See Figure 6 for details. CT OF SLAVE(S) IS 1.25 CT OF MASTER. CT CT MASTER LTC1922-1 SYNC 5.1k 1k 5.1k 1k LTC1922-1 LTC1922-1 SYNC CT CT CT CT SLAVES 1922 F06a Figure 6a. SYNC Output (Master Mode) AMPLITUDE > 1.8V 12.5ns < PW < 0.4/ EXTERNAL FREQUENCY SOURCE 1k SYNC 5.1k LTC1922-1 CT CT Figure 6b. SYNC Input from an External Source 3. Slope compensation is required for most peak current mode controllers in order to prevent subharmonic oscillation of the current control loop. In general, if the system duty cycle exceeds 50% in a fixed frequency, continuous current mode converter, an unstable condition exists within the current control loop. Any perturbation in the current signal is amplified by the PWM modulator resulting in an unstable condition. Some common manifestations of this include alternate pulse nonuniformity and pulse width jitter. Fortunately, this can be addressed by adding a corrective slope to the current sense signal or by subtracting the same slope from the current command signal (error amplifier output). In theory, the current doubler output configuration does not require slope compensation since the output inductor duty cycles only approach 50%. However, transient conditions can momentarily cause higher duty cycles and therefore, the possibility for unstable operation. The exact amount of required slope compensation is easily programmed by the LTC1922-1 with the addition of a single external resistor (see Figure 7). The LTC1922-1 generates a current that is proportional to the instantaneous voltage on C T , 14 U SYNC * * 5.1k * UP TO 5 SLAVES (33A/V(CT)). Thus, at the peak of CT, this current is approximately 125A and is output from the CS pin. A resistor connected between CS and the external current sense resistor sums in the required amount of slope compensation. The value of this resistor is dependent on several factors including minimum VIN, VOUT, switching frequency, current sense resistor value and output inductor value. An illustrative example with the design equation is provided below. Example: VIN = 36V to 72V VOUT = 3.3V IOUT = 40A L = 2.2H Transformer turns ratio (N) = VIN(MIN) * DMAX/ VOUT = 3 RCS = 0.025 fSW = 300kHz, i.e., transformer f = fSW/2 = 150kHz RSLOPE = VO * RCS/(2 * L * fT * 125A * N) = 3.3V * 0.025/ (2 * 2.2A * 100k * 125A * 3) RSLOPE = 500, choose the next higher standard value to account for tolerances in ISLOPE, RCS, N and L. LTC1922-1 CT I= V(CT) 33k RSLOPE RCS BRIDGE CURRENT CS 1922 F06b 33k ADDED SLOPE CURRENT SENSE WAVEFORM 1922 F07 Figure 7. Slope Compensation Circuitry Current Sensing and Overcurrent Protection Current sensing provides feedback for the current mode control loop and protection from overload conditions. The LTC1922-1 is compatible with either resistive sensing or current transformer methods. Internally connected to the LTC1922-1 CS pin are two comparators that provide pulse-by-pulse and overcurrent shutdown functions respectively. (See Figure 8) LTC1922-1 OPERATIO Figure 8. Current Sense/Fault Circuitry Detail The pulse-by-pulse comparator has a 400mV nominal threshold, which can reduce sense resistor losses by 67% compared to previous solutions. This corresponds to 3W in a 200W, 48V to 3.3V converter. If the 400mV threshold is exceeded, the PWM cycle is terminated. The overcurrent comparator is set approximately 50% higher than the pulse-by-pulse level. If the current signal exceeds this level, the PWM cycle is terminated, the soft-start capacitor is quickly discharged and a soft-start cycle is initiated. If the overcurrent condition persists, the LTC1922-1 halts PWM operation and waits for the soft-start capacitor to charge up to approximately 4V before a retry is allowed. The soft-start capacitor is charged by an internal 12A current source. If the fault condition has not cleared when soft-start reaches 4V, the soft-start pin is again discharged and a new cycle is initiated. This is referred to as hiccup mode operation. In normal operation and under most abnormal conditions, the pulse-by-pulse comparator is fast enough to prevent hiccup mode operation. In severe cases, however, with high input voltage, very low RDS(ON) MOSFETs and a shorted output, or with saturating magnetics, the overcurrent comparator provides a means of protecting the power converter. Leading Edge Blanking The LTC1922-1 provides programmable leading edge blanking to prevent nuisance tripping of the current sense circuitry. Although the ZVS full-bridge topology is somewhat more immune to leading edge noise spikes than other types of converters, they are not totally eliminated. Leading edge blanking relieves the filtering requirements for the CS pin, greatly improving the response to real overcurrent conditions. It also allows the use of a ground referenced current sense resistor or transformer(s), further simplifying the design. With a single 10k to 100k resistor from RLEB to GND, blanking times of approximately 40ns to 320ns are programmed. If not required, connecting RLEB to VREF can disable leading edge blanking. Keep in mind that the use of leading edge blanking will set a minimum linear control range for the phase modulation circuitry. Resistive Sensing A resistor connected between input common and the sources of MB and MD is the simplest, fastest and most accurate method of current sensing for the full-bridge converter. This is the preferred method for low to moderate power levels. A graph of resistive sense power losses vs output power is shown Figure 9. The sense resistor should be chosen such that the maximum rated output current for the converter can be delivered at the lowest expected VIN. Use the following formula to calculate the optimal value for RCS. + UVLO ENABLE R - 600mV - SQ + - U PULSE BY PULSE CURRENT LIMIT MOD + CS 400mV - PWM LATCH Q S PWM LOGIC UVLO ENABLE SQ R H = SHUTDOWN OUTPUTS Q RCS OVERLOAD CURRENT LIMIT + 4.1V 12A SS 0.4V CSS Q 1922 F08 15 LTC1922-1 OPERATIO 2.0 RS = 0.025 1.8 VIN = 48V VO = 3.3V 1.6 LO = 2.2H 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 10 15 20 25 30 OUTPUT CURRENT (A) 35 40 1922 * F09 POWER LOSS (W) Figure 9. RSENSE Power Loss vs IOUT If RAMP and CS are connected together: RCS = 0.4V - (125A * RSLOPE) IP (PEAK) IP (PEAK) = IO(MAX) LMAG * f CLK 2 * N * EFF VO (1 - DMIN ) LOUT * f CLK* N where: N = Transformer turns ratio If RAMP and CS are separated RCS 0.4V = IP (PEAK) Current Transformer Sensing A current sense transformer can be used in lieu of resistive sensing with the LTC1922-1. Current sense transformers are available in many styles from several manufacturers. A typical sense transformer for this application will use a 1:50 turns ratio (N), so that the sense resistor value is N times larger, and the secondary current N times smaller than in the resistive sense case. Therefore, the sense resistor power loss is about N times less with the transformer method, neglecting the transformers core and copper losses. The disadvantages of this approach 16 U + VIN(MAX) * 2 * DMIN + include, higher cost and complexity, lower accuracy, core reset/max duty cycle limitations and lower speed. Nevertheless, for very high power applications, this method is preferred. The sense transformer primary is placed in the same location as the ground referenced sense resistor, or between the upper MOSFET drains in the (MA, MC) and VIN. The advantage of the high side location is a greater immunity to leading edge noise spikes, since gate charge current and reflected rectifier recovery current are largely eliminated. Figure 10 illustrates a typical current sense transformer based sensing scheme. RS in this case is calculated the same as in the resistive case, only its value is increased by the sense transformer turns ratio. At high duty cycles, it may become difficult or impossible to reset the current transformer. This is because the required transformer reset voltage increases as the available time for reset decreases to equalize the (volt * seconds) applied. The interwinding capacitance and secondary inductance of the current sense transformer form a resonant circuit that limits the dV/dT on the secondary of the CS transformer. This in turn limits the maximum achievable duty cycle for the CS transformer. Attempts to operate beyond this limit will cause the transformer core to "walk" and eventually saturate, opening up the current feedback loop. Common methods to address this limitation include: 1. Reducing the maximum duty cycle by lowering the power transformer turns ratio. 2. Reducing the switching frequency of the converter. 3. Employ external active reset circuitry. 4. Using two CS transformers summed together. 5. Choose a CS transformer optimized for high frequency applications. MB SOURCE RSLOPE RAMP RS CS OPTIONAL FILTERING N:1 CURRENT TRANSFORMER MD SOURCE 1922 F10 Figure 10. Current Transformer Sense Circuitry LTC1922-1 OPERATIO Phase Modulator The LTC1922-1 phase modulation control circuitry is comprised of the phase modulation comparator and logic, the error amplifier, and the soft-start amplifier (see Figure 11). Together, these elements develop the required phase overlap (duty cycle) required to keep the output voltage in regulation. In isolated applications, the sensed output voltage error signal is fed back to COMP across the input to output isolation boundary by an optical coupler and shunt reference/error amplifier (LT(R)1431) combination. The FB pin is connected to GND, forcing COMP high. The collector of the optoisolator is connected to COMP directly. The voltage COMP is internally attenuated by the LTC1922-1. The attenuated COMP voltage provides one input to the phase modulation comparator. This is the current command. The other input to the phase modulation comparator is the RAMP voltage, level shifted by approximately 400mV. This is the current loop feedback. During every switching cycle, alternate diagonal switches U (MA-MD or MB-MC) conduct and cause current in an output inductor to increase. This current is seen on the primary of the power transformer divided by the turns ratio. Since the current sense resistor is connected between GND and the two bottom bridge transistors, a voltage proportional to the output inductor current will be seen across RSENSE. The high side of RSENSE is also connected to RAMP and CS, usually through a small resistor (RSLOPE). When the voltage on RAMP/CS exceeds either COMP/5.2 - 400mV, or 400mv, the overlap conduction period will terminate. During normal operation, the attenuated COMP voltage will determine the RAMP/CS trip point. During start-up, or slewing conditions following a large load step, the 400mV CS threshold will terminate the cycle, as COMP will be driven high, such that the attenuated version exceeds the 400mV threshold. In extreme conditions, the 600mV threshold on CS will be exceeded, invoking a soft-start/restart cycle. FB 1.2V COMP VREF 12A SS + - 14.9k RLEB RAMP BLANKING QS R CLK 1922 F11 + - ERROR AMPLIFIER PHASE MODULATION COMPARATOR - + TOGGLE F/F Q CLK Q PHASE MODULATION LOGIC SQ CLK R A B 50k C D + SOFT-START AMPLIFIER 400mV - FROM CURRENT LIMIT COMPARATOR Figure 11. Phase Modulation Circuitry 17 LTC1922-1 OPERATIO Selecting the Power Stage Components Perhaps the most critical part of the overall design of the converter is selecting the power MOSFETs, transformer, inductors and filter capacitors. Tremendous gains in efficiency, transient performance and overall operation can be obtained as long as a few simple guidelines are followed with the phase shifted full-bridge topology. Power Transformer This guide is aimed at selecting readily available standard "off the shelf" transformers. The basic requirements, however, apply to custom transformer designs as well. Switching frequency, core material characteristics, series resistance and input/output voltages all play an important role in transformer selection. Close attention also needs to be paid to leakage and magnetizing inductances as they play an important role in how well the converter will achieve ZVS. Planar magnetics are very well suited to these applications because of their excellent control of these parameters. Turns Ratio The required turns ratio for a current doubler secondary is given below. Depending on the magnetics selected, this value may need to be reduced slightly. Turns ratio formula: N = 2* where: VIN(MIN) = Minimum VIN for operation DMAX = Maximum duty cycle of controller Magnetizing, Output, and Leakage Inductors A lower value of magnetizing and output inductance will improve the ability of the converter to achieve ZVS over the full range of loads and reduce the size of the external commutating inductor. One of the trade-offs is increased primary referred ripple current which has a small negative LCOM vs ZVS vs Load LCOM + LL = 4 / 3 C OSS * LMAG * f SW 2 * D2 2 2 VIN(MIN) * DMAX VOUT where: TR = transformer reset time (worst case) = IO(MAX) * f SW * LMAG + VIN * 2 * D * N LCOM + LL f SW * LMAG * N VIN 18 U impact on efficiency. Other factors to consider are switching frequency and required maximum duty cycle. A lower value of magnetizing inductance will require a longer time to reset the core, cutting into the available duty cycle range. As switching frequencies increase, this becomes more significant. In general, the magnetizing inductance value should be the lowest value required in order to achieve the necessary maximum duty cycle at the chosen switching frequency. Output inductor value determines the magnitude of output ripple current and therefore the ripple voltage along with the output capacitors. Generally speaking, the output inductance should be minimized as much as possible in order to improve transient response. In addition, output capacitance ESR should be minimized as much as possible. Using the equations below, plug in the manufacturers magnetizing inductance value and a "starting value" of commutating inductance (1% of LMAG) to verify that a sufficient max duty cycle can be achieved at the desired switching frequency. Next, use equation (2) to determine what the absolute minimum required LCOM is to guarantee ZVT over the entire load range. One or two iterations may be required in order to arrive at the final selections. MAX DC vs LCOM at fSW MAX DC 2 - f SW * TR ; 2 (1) (2) LTC1922-1 OPERATIO where: COSS = MOSFET D-S capacitance lMAG = magnetizing inductance fSW = switching frequency D = duty cycle LL = leakage inductance For a 48V to 3.3V/5V, 200W converter, the following values were derived: fSW LMAG LCOM LOUT : 300kHz : 100H : 0.9H : 2.2H Turns Ratio (N) = 2.5 Output Capacitors Output capacitor selection has a dramatic impact on ripple voltage, dynamic response to transients and stability. Capacitor ESR along with output inductor ripple current will determine the peak-to-peak voltage ripple on the output. The current doubler configuration is advantageous because it has inherent ripple current reduction. The dual output inductors deliver current to the output capacitor 180 degrees out of phase, in effect, partially canceling each other's ripple current. This reduction is maximized at high duty cycle and decreases as the duty cycle reduces. This means that a current doubler converter requires less output capacitance for the same performance as a conventional converter. By determining the minimum duty cycle for the converter, worse-case VOUT ripple can be derived by the formula given below. VORIPPLE = IRIPPLE * ESR = where: D = minimum duty cycle fSW = oscillator frequency LO = output inductance ESR = output capacitor series resistance VO * ESR (1 - D)(1 - 2D) LO * 2 * f SW U The amount of bulk capacitance required is usually system dependent, but has some relationship to output inductance value, switching frequency, load power and dynamic load characteristics. Polymer electrolytic capacitors are the preferred choice for their combination of low ESR, small size and high reliability. For less demanding applications, or those not constrained by size, aluminum electrolytic capacitors are commonly applied. Most DC/DC converters in the 100kHz to 300kHz range use 20F to 25F of bulk capacitance per watt of output power. Converters switching at higher frequencies can usually use less bulk capacitance. In systems where dynamic response is critical, additional high frequency capacitors, such as ceramics, can substantially reduce voltage transients, Power converter stability is, to a large extent, determined by the choice of output capacitor. A zero in the converter's transfer function is given by 1/(2 * ESR * CO). Aluminum electrolytic ESR is highly variable with temperature, increasing by about 4x at cold temperatures, making the ESR zero frequency highly variable. Polymer electrolytic ESR is essentially flat with temperature. This characteristic simplifies loop compensation and allows for a much faster responding power supply compared to one with aluminum electrolytic capacitors. Specific details on loop compensation are given in the Compensation section of the data sheet. Power MOSFETs The full-bridge power MOSFETs should be selected for their RDS(ON) and BVDSS ratings. Select the lowest BVDSS rated MOSFET available for a given input voltage range leaving at least a 20% voltage margin. Conduction losses are directly proportional to RDS(ON). Since the full-bridge has two MOSFETs in the power path most of the time, conduction losses are approximately equal to: 2 * RDS(ON) * I2, where I = IO/2N Switching losses in the MOSFETs are dominated by the power required to charge their gates, and turn-on and turn-off losses. At higher power levels, gate charge power is seldom a significant contributor to efficiency loss. ZVS operation virtually eliminates turn-on losses. Turn-off losses are reduced by the use of an external drain to source 19 LTC1922-1 OPERATIO snubber capacitor and/or a very low resistance turn-off driver. If synchronous rectifier MOSFETs are used on the secondary, the same general guidelines apply. Keep in mind, however, that the BVDSS rating needed for these can be greater than VIN(MAX)/N, depending on how well the secondary is snubbed. Without snubbing, the secondary voltage can ring to levels far beyond what is expected due to the resonant tank circuit formed between the secondary leakage inductance and the COSS (output capacitance) of the synchronous rectifier MOSFETs. Switching Frequency Selection Unless constrained by other system requirements, the power converter's switching frequency is usually set as high as possible while staying within the desired efficiency target. The benefits of higher switching frequencies are many including smaller size, weight and reduced bulk capacitance. In the full-bridge phase shift converter, these principles are generally the same with the added complication of maintaining zero voltage transitions, and therefore, higher efficiency. ZVS is achieved in a finite time during the switching cycle. During the ZVS time, power is not delivered to the output; the act of ZVS reduces the maximum available duty cycle. This reduction is proportional to maximum output power since the parasitic capacitive element (MOSFETs) that increase ZVS time get larger as power levels increase. This implies an inverse relationship between output power level and switching frequency. Table 1 displays recommended maximum switching frequency vs power level for a 30V/75V in to 3.3V/5V out converter. Higher switching frequencies can be used if the input voltage range is limited, the output voltage is lower and/or lower efficiency can be tolerated. Table 1.Switching Frequency vs Power Level <50W <100W <200W <500W <1kW <2kW 600kHz 450kHz 300kHz 200kHz 150kHz 100kHz 20 U Closing the Feedback Loop Closing the feedback loop with the full-bridge converter involves identifying where the power stage and other system poles/zeroes are located and then designing a compensation network around the converters error amplifier to shape the frequency response to insure adequate phase margin and transient response. Additional modifications will sometimes be required in order to deal with parasitic elements within the converter that can alter the feedback response. The compensation network will vary depending on the load current range and the type of output capacitors used. In isolated applications, the compensation network is generally located on the secondary side of the power supply, around the error amplifier of the optocoupler driver, usually an LT1431or equivalent. In nonisolated systems, the compensation network is located around the LTC1922-1's error amplifier. In current mode control, the dominant system pole is determined by the load resistance (VO/IO) and the output capacitor 1/(2 * RO * CO). The output capacitors ESR 1/(2 * ESR * CO) introduces a zero. Excellent DC line and load regulation can be obtained if there is high loop gain at DC. This requires an integrator type of compensator around the error amplifier. A procedure is provided for deriving the required compensation components. More complex types of compensation networks can be used to obtain higher bandwidth if necessary. Step 1. Calculate location of minimum and maximum output pole: FP1(MIN) = 1/(2 * RO(MAX) * CO) FP1(MAX) = 1/(2 * RO(MIN) * CO) Step 2. Calculate ESR zero location: FZ1 = 1/(2 * RESR * CO) Step 3. Calculate the feedback divider gain: RB/(RB + RT) or VREF/VOUT If Polymer electrolytic output capacitors are used, the ESR zero can be employed in the overall loop compensation and optimum bandwidth can be achieved. If aluminum electrolytics are used, the loop will need to be rolled off prior to the ESR zero frequency, making the loop response LTC1922-1 OPERATIO slower. A linearized SPICE macromodel of the control loop is very helpful tool to quickly evaluate the frequency response of various compensation networks. Polymer Electrolytic (see Figure 12) 1/(2CCRI) sets a low frequency pole. 1/(2CCRF) sets the low frequency zero. The zero frequency should coincide with the worstcase lowest output pole frequency. The pole frequency and mid frequency gain (RF/RI) should be set such so that the loop crosses over zero dB with a -1 slope at a frequency lower than (fSW/8). Use a bode plot to graphically display the frequency response. An optional higher frequency pole set by CP2 and Rf is used to attenuate switching frequency noise. VOUT COMP OPTO OPTIONAL Rf CO RL ESR RD 2.5V RI REF - + COLL CC VOUT CP2 Figure 12. Compensation for Polymer Electrolytic Aluminum Electrolytic (see Figure 12) the goal of this compensator will be to cross over the output minimum pole frequency. Set a low frequency pole with CC and RIN at a frequency that will cross over the loop at the output pole minimum F, place the zero formed by CC and Rf at the output pole F. Synchronous Rectification The LTC1922-1 produces the precise timing signals necessary to control current doubler secondary side synchronous MOSFETs on OUTE and OUTF. Synchronous rectifiers are used in place of Schottky or Silicon diodes on the secondary side of the power supply. As MOSFET RDS(ON) levels continue to drop, significant efficiency improvements can be realized with synchronous rectification, provided that the MOSFET switch timing is optimized. An additional benefit realized with synchronous rectifiers is bipolar output current capability. These characteristics improve transient response, particularly overshoot, and improve ZVS ability at light loads. U Current Doubler The current doubler secondary employs two output inductors that equally share the output load current. The transformer secondary is not center-tapped. This configuration provides 2x higher output current capability compared to similarly sized single output inductor modules, hence the name. Each output inductor is twice the inductance value as the equivalent single inductor configuration and the transformer turns ratio is 1/2 that of a single inductor secondary. The drive to the inductors is 180 degrees out of phase which provides partial ripple current cancellation in the output capacitor(s). Reduced capacitor ripple current lowers output voltage ripple and enhances the capacitors's reliability. The amount of ripple cancellation is related to duty cycle (see Figure 13). Although the current doubler requires an additional inductor, the inductor core volume is proportional to LI2, thus the size penalty is small. The transformer construction is simplified without a center-tap winding and the turns ratio is reduced by 1/2 compared to a conventional full wave rectifier configuration. 1 NOTE: INDUCTOR(S) DUTY CYCLE IS LIMITED TO 50% WITH CURRENT DOUBLER PHASE SHIFT CONTROL. LT1431 OR EQUIVALENT PRECISION ERROR AMP AND REFERENCE 1922 F12 NORMALIZED OUTPUT RIPPLE CURRENT ATTENUATION 0 0 0.25 DUTY CYCLE 0.5 1922 * F13 Figure 13. Ripple Current Cancellation vs Duty Cycle Synchronous rectification of the current doubler secondary requires two ground referenced N-channel MOSFETs. The timing of the LTC1922-1 drive signals is shown in the Timing Diagram. Synchronous rectifier turn-on is internally delayed by the LTC1922-1 after OUT (C or D) turn-off--just after the end of a power cycle. Synchronous rectifier turn-off occurs coincident with OUT (A or B) turn-off. This gives a passive transition time margin before 21 LTC1922-1 OPERATIO the start of a new power cycle. A noninverting MOSFET driver such as the LTC1693-1 (Figure 14) is used so that a single signal transformer with secondary center tap can be employed to translate the drive signals from the primary to the secondary side. In the event of overcurrent shutdown, or UVLO condition, both synchronous rectification MOSFETs are driven on in order to protect the load circuitry. Full-Bridge Gate Drive The full-bridge converter requires high current MOSFET gate driver circuitry for two ground referenced switches and two high side referred switches. Providing drive to the ground referenced switches is not too difficult as long as the traces from the gate driver chip or buffer to the gate and source leads are short and direct. Drive requirements are LTC1922-1 1:2 OUTE 22 U further eased since all of the switches turn on with zero VDS, eliminating the "Miller" effect. Low turn-off resistance is critical, however, in order to prevent excessive turn-off losses resulting from the same Miller effects that were not an issue for turn on. The LTC1922-1 does not require the propagation delays of the high and low side drive circuits to be precisely matched as the DirectSense ZVS circuitry will adapt accordingly, unlike previous solutions. As a result, LTC1922-1 can drive a simple NPN-PNP buffer or a gate driver chip like the LTC1693-1 to provide the low side gate drive. Providing drive to the high side presents additional challenges since the MOSFET gate must be driven above the input supply. A simple circuit (Figure 15) using a single LTC1693-1, an inexpensive signal transformer, and a few discrete components provides both high side gate drives (A and C) reliably. LTC1693-1 OUT1 IN1 GND1 OUTF GND2 IN2 OUT2 1922 F14 Figure 14. Isolated Drive Circuitry REGULATED BIAS LTC1922-1 0.1F 0.1F OUTA OR OUTC 2k BAT 54 IN VCC OUT VIN 2F CER POWER MOSFET 1/2 LTC1693-1 GND SIGNAL TRANSFORMER BRIDGE LEG 1922 F15 Figure 15. High Side Gate Driver Circuitry LTC1922-1 PACKAGE DESCRIPTIO 5.20 - 5.38** (0.205 - 0.212) 0.13 - 0.22 (0.005 - 0.009) 0.55 - 0.95 (0.022 - 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.300 - 0.325 (7.620 - 8.255) 0.009 - 0.015 (0.229 - 0.381) 0.020 (0.508) MIN ( +0.035 0.325 -0.015 +0.889 8.255 -0.381 ) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimensions in inches (millimeters) unless otherwise noted. G Package 20-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 7.07 - 7.33* (0.278 - 0.289) 20 19 18 17 16 15 14 13 12 11 7.65 - 7.90 (0.301 - 0.311) 1 2 3 4 5 6 7 8 9 10 1.73 - 1.99 (0.068 - 0.078) 0 - 8 0.65 (0.0256) BSC 0.25 - 0.38 (0.010 - 0.015) 0.05 - 0.21 (0.002 - 0.008) G20 SSOP 1098 N Package 20-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.040* (26.416) MAX 20 19 18 17 16 15 14 13 12 11 0.255 0.015* (6.477 0.381) 1 0.130 0.005 (3.302 0.127) 2 3 4 5 6 7 8 9 10 0.045 - 0.065 (1.143 - 1.651) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.127) MIN 0.100 (2.54) BSC 0.018 0.003 (0.457 0.076) N20 1098 23 LTC1922-1 TYPICAL APPLICATIO 10V D2 BAS21 R3 470 R5 2.2k D3 BAT54 C3 2.2F D1 BAS21 Synchronous Phase Shifted Full Bridge 48V to 3.3V, 40A Isolated Converter Q1 8 1 VCC1 IN1 VCC2 6 C1 2.2F A R1 10 Q2 FMMT718 VLOW C8, 1nF 100V R2 10k 0.125W C7 + 470F 6V C4 + 470F 6V L2 2.4H +VOUT 7 OUT1 U1 LTC1693-1 5 3 OUT2 IN2 4 2 GND1 GND2 R7 2.2k D4 BAT54 R8 470 R6 470 C12 0.1F T2 TTWB-1010 C14 0.1F T3 TTWB-1010 +VIN C5 1.5F 100V -VIN A L1 4.7H C10 1.5F 100V C2 1.5F 100V R12 13.3k 1% R16 13.3k 1% R25 1k 1% 9 SBUS 15 C27 0.1F VIN SYNC 1 5.1k VREF 11 C29 1F R35 3.3k 10 ADLY C6 1.5F 100V 10V D15 1N4683 3V D14 1N4699 12V R29 510 R20 310k R23 30k R24 10k C28 68F 20V + RELATED PARTS PART NUMBER LT1105 LT1681/LTC1698 DESCRIPTION Off-Line Switching Regulator 36V to 72V Input Isolated DC/DC Converter Chipset COMMENTS Built-In Isolated Regulation without Optoisolator Synchronous Rectification; Overcurrent, Overvoltage, UVLO Protection; Power Good Output Signal;h Voltage Margining; Compact Solution Minimizes Conducted and Radiated EMI; Reduces Need for Filters, Shields and PCB Iterations 1.5A Peak Output Current; 4.5V VIN 13.2V 48V to 5V Conversion; No Optoisolator Required 1922f LT/TP 0501 2K * PRINTED IN USA LT1683 LTC1693-1 LT1725 Ultralow Noise Push-Pull DC/DC Converter High Speed Dual MOSFET Driver General Purpose Isolated Flyback Controller 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U Q3 R4 10 Q4 FMMT718 10V Q6 FMMT619 Q11 Q13 FMMT718 R10 470 Q14 FMMT718 Q12 R9 0.06 1W VHIGH BAS21 BAS21 7T R18 470 0.125W C16 1nF R19 4.7k D11 BAT54 R22 950 0.125W VLOW U2 8 LTC1693-1 6 VCC1 VCC2 3 5 IN2 OUT2 1 7 IN1 OUT1 2 4 GND2 GND1 Q15 FZT600 C20 1F D12 MMSZ4240BT1 10V C21 4.7F D6 BAS21 R15 2k 0.125W R11 10 0.125W C15 2.2nF 250V AC "Y" P L4 2.2H 8T 2T L3 2.4H VHIGH 10V Q5 FMMT619 + Q7 C9 470F 6V + C11 470F 6V Q10 Q9 Q8 D6 BAS21 10V 22F 25V + L5 1mH T4, TTWB-1010 C18 R21 0.1F 3.3 0.125W C22 R28 0.1F 3.3 0.125W C19 1nF T5, TTWB-1010 R27 4.7k D13 BAT54 D16 C1, C3 TAIYO YUDEN EMK316BJ225ML (X5R, 16V, 1206) C2, C5, C6, C10 VITRAMON VJ1825Y155MXB(X7R, 1825) C4, C7, C9, C11 KEMET T510X477M006AS (TANT, 7343H) C15 MU RATA GHM3035C7R222K-GC (X7R, 2220) C17 TAIYO YUDEN UMK316BJ224ML (X7R,1206) C20, C29 TAIYO YUDEN UMK316BJ105ML (X7R,1206) C28 AVX TPSE686M020R0125 (TANT 7343H) C21 TAIYO YUDEN EMK325BJ475MN (X5R, 1210) R9 DALE WSL L1 COILCRAFT DO3316P-472 L5 COILCRAFT DO1608C-105 L2, L2 PULSE P1977 PQ20/20 1.25mohms 20A Q7, Q8, Q9, Q10 SUD50N03 Q1, Q3, Q11, Q12 SUD30N10-25 C17 0.22F 50V - VOUT R13 13.3k 1% C33 0.1F R17 13.3k 1% R26 1k 1% 18 DRVA P C34 0.1F C23 100pF 8 16 DRVC 2 17 14 R14 510 3 NOTE: UNLESS OTHERWISE NOTED ALL CAPS 25V ALL RESISTORS 1206, 5% ALL DIODES MMBT914LT1 ALL NPNs MMBT3904LT1 ALL PNPs MMBT3906LT3 +VOUT PDLY RAMP DRVB DRVD CS 12 OUTF 13 OUTE 46 COMP U3 LTC1922-1 CT 20 C30 180pF RLEB 5 R34 20k GND 19 SS 7 C31 0.068F R30 ISO1 470 MOC207 7431 C25 C24 0.1F 0.01F 1 FB 6 5 8 2 R36 100k U4 LT1431 3 COLL V+ 2 6 GNDF COMP 4 5 GNDS RTOP 8 7 RMID REF R31 7.5k R33 3.01k 1% R32 10k C26 0.02F R37 9.3k 1% - VOUT 1922 TA02 (c) LINEAR TECHNOLOGY CORPORATION 2000 |
Price & Availability of LTC1922-1
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